Chapter 1. LITERATURE REVIEW

1.1 Simulation of power

electronic circuits

To simulate a power electronic circuit or any

electrical circuit, there are a few procedures that are required to be followed.

At first a mathematical model of the circuit under test is formed, then the

circuit is represented by some mathematical or network equations and finally

some techniques are chosen to solve those equations. After a proper model is

chosen the mathematical equations for the model can be developed by using

Maxwell’s cyclic current, widely known as Kirchhoff’s Voltage Law (KVL), nodal

analysis or Kirchhoff’s Current Law (KCL) and the relatively newer approach

called Modified Nodal Analysis (MNA). Nodal analysis had some advantages over

mesh analysis, one being reduced number of equations compared to mesh analysis.

But there were difficulties in the use of the classical nodal analysis particularly

in computer simulation; certain elements such as voltage sources, dependent

sources, transformers etc. could not be included in the analysis unless some conversion

was done to some extent but on conversion there was always loss of information

about the model 1. MNA was proposed by Chung-Wen Ho, in 1975 2, 3

to resolve the limitations of the classical nodal analysis. MNA can

considerably reduce computation time for solving the network matrices and is

easier to implement on a computer thus making it more suitable for simulation

of electrical circuits. Real Time Simulation (RTS) of power electronic circuits

demands even faster computation times and MNA was further upgraded to a Fixed

Admittance Modified Nodal Analysis Method (FAMNM) 4, 5. This method allowed

the system equations to be solved in very small time steps as required by RTS

of fast switching power electronic converters.

1.2 Real Time Simulation

Whenever a computer simulation of a computer model

of any physical process or a system is done in parallel to its physical

counterpart can be referred to as the Real Time Simulation (RTS). The virtual representation of physical system i.e. a

virtual model runs simultaneously and also for the same time as the physical

system. They may share common input variables and come out with comparable

output. One good example for a RTS can be operation of the Fuel

Injection System of a modern day computer controlled car engine, the onboard

computer (Engine Control Unit) calculates the duration of operation and the

interval between each operation based upon the throttle input, camshaft

position, inputs from Oxygen Sensors, inputs from NOx sensors etc. all of which

are measured in real time.

A computer does all the computations using an

operating system which eventually does all of its calculations in the form of

0’s and 1’s. All the differential equations, state equations or any

mathematical functions representing a physical system will converted to a

discrete system of 0’s and 1’s, these will be solved by the computer simulation

software using their own solvers. The solvers use different numerical methods

to do the computations and each may take different amount of time and produce

results with different accuracy.

To work with RTS the simulation associated would

be for discrete time with a constant step size. Variable time-steps simulation

is not suitable for RTS and hence the time is incremented in equal step sizes

called Simulation Time Steps and the simulation itself is often called Fixed

Time Simulation.

As mentioned earlier the differential equations

and the mathematical functions representing the model are solved to perform the

I/O operations and to obtain the output of the model. However during a

‘discrete non real time simulation’ the actual time required to solve the

aforementioned equations and functions may be more or less than the simulation

time step. But in case of real time simulation it is necessary that (apart from

the precise modeling of the physical system) all the computations are done

within the simulation time step so that the model under test can accurately

represent the functioning and perform all the I/O operations of its equivalent

real or physical system.

If the computations are not complete within the

simulation time step the real time simulation results are not accurate, which

is also referred to as an ‘overrun’. Moreover, if the computations are done

before the simulation time step is complete then the remaining time, called the

‘idle-time’ 7 is simply lost, which is in contrast to the accelerated

simulations where the remaining time would be utilized to perform the

computations of the subsequent time step. Fig. 1.1. to Fig. 1.3. distinguishes

between the characteristics of a real time and non-real time simulations.

Fig. 1. 1. Timing

diagram when Computation Time is less than Simulation Time Step (non-real time)

Fig. 1. 2. Timing

diagram when Computation Time is greater than Simulation Time Step (non-real time)

Fig. 1. 3. Timing

diagram during Real Time Simulation

1.3 Selection of the real time simulator

As suggested in 7-12 selection of real time

simulators can be done based upon the applications to which they are intended for

and can be categorized as:

Rapid Control Prototyping

(RCP):

In a Rapid Control Prototyping a physical setup

is always used and the controller is implemented in a real time simulator. The

presence of a virtual controller enables it to be configured with more

flexibility and be debugged easily. Since the modelling and testing of the

controller becomes easy and fast, the prototype model of the controller can be

developed sooner to a final robust product.

Hardware in the Loop (HIL):

In Hardware in the Loop a virtual model of the

physical system is run on a real time simulator this virtual model emulates and

behaves like a physical test bench; this virtual model is then controlled by a

physical controller. In a variation of HIL, another real time simulator can

function as a physical controller and feed the virtual model in a separate

simulator. This configuration is very beneficial because the physical

controller can be tested even without a physical setup, the tests are very

repeatable and can be done without any fear of damage as in case of a real

hardware based setup. The work in this literature uses Hardware in the Loop

(HIL)

Software in the Loop (SIL):

Software in the Loop is possible as the

simulators grow more and more powerful. This allows the controller and the

virtual plant model to be implemented in the same real time simulator. Here no

physical input/outputs (I/O) are used and that ensures that the fidelity of the

signals are maintained. Moreover the simulations can now run only in the

virtual mode and there are no constraints in following the time clock of the

real world. Simulation can now take their own time and if resources are

available simulations can run faster than the real world time while maintaining

the integrity of the results.

1.4 CPU and FPGA Based Simulation

The computer architecture has changed a lot in the last two

decades, the advent of multiple cores, increase in parallel processing

capabilities, decrease in the I/O latencies, faster working memories and

improved hardware interfaces 13 have made the modern computer quite suitable

for real time simulations. Fig. 1.4. shows an Intel chipset architecture widely

used until 2011, Fig. 1.5. shows an architecture used currently in most modern

computers.

Fig. 1. 4. Computer

chipset architecture prevalent before Sandy Bridge microarchitecture introduced

in 2011

Fig. 1. 5. Modern

computer chipset using Nehalem microarchitecture

However, even though the CPU of a modern

computer has a very high clock frequency the sequential nature of the operating

system and the latencies still present at the i/o communications buses/ports

allows it to have a minimal sampling time of about 5-10 ?s. This sampling time

is often enough for the real time simulation of systems with slower dynamics

such as a motor but for fast systems like the high frequency switches in the

power electronic systems, this sampling rate is inadequate. So a methodology

was developed wherein the models requiring very low sampling times are

simulated in Field Programmable Logic Gate Arrays (FPGAs) 14 – 16, the

highly parallel structure of the FPGA allowed very high sampling rates with

simulation time steps as low as 250ns. Fig. 1.6. shows a CPU based simulation

and Fig. 1.7. shows a FPGA based simulation.

Fig. 1. 6. CPU

Based Simulation

Fig. 1. 7. FPGA

Based Simulation

1.5 Discrete Time Switch Model in Real Time

Simulation

There are a number of models for representing a switch

in order to make it suitable for computer simulations. Some simulators model

the switch as a small resistance when it is ON and a large resistance when it

is OFF 5, the value of the ON and OFF resistances are updated at every step

of the iteration in the numerical method used for the simulation 5. The

trouble with this approach is that for a large network with a number of

switches huge amount of computational resources may be consumed for the updating

of the resistance parameters at every step of the simulation. 17 proposes a

model with a RC circuit for an open circuit and an inductor for a short

circuit, this representation removes the need of a system matrix inversion when

the switch state changes from ON to OFF or OFF to ON. Another model proposed in

18 represents the switch as a resistance across a capacitance, when the

switch turns ON this resistance goes low and goes high when it is turned OFF.

In the switch model mentioned in 5 an ideal

switch is modelled as a conductance in parallel with a current source. This

conductance will not change with the iteration steps and the current source

shall provide details of the state of the switch. The work in this thesis shall

consider this model for real time simulation.

1.6

Validation of Power Electronic Circuits

Validation of power electronic systems is

necessary to ensure that a virtual model behaves like a real physical system to

the extent possible. Real time simulation of fast switching power electronic

converters using a FPGA based ‘Electric Hardware Solver (eHS) 8 is discussed

in 16. The design flow for the solver as well as validation results of the

RTS of a number of power electronic converters are also covered. The results

were validated by comparing the output of the eHS with those from the solver of

SimPowerSystems (SPS). Some of the shortcomings of this method of simulating

fast switching devices has also been discussed. Notwithstanding the

shortcomings the technique of performing real time simulation of power

electronic systems in FPGAs has a lot of potential.

1.7

Multilevel Inverters

An introduction to the different topologies and

working principles of multilevel converters are covered in 20. A more

detailed overview about NPC inverters along with the modulation techniques is

provided in 21. Different modulation schemes for a three level inverter are

introduced in 22. A comprehensive working of the three level NPC inverter is

discussed in 23, 24, this will also be covered in detail in the Chapter 3

along with a step by step procedure in the hardware validation of the same. The

results obtained from the simulation of a three phase three level inverter in

SimScape Power Systems (SPS), a FPGA based electrical Hardware Solver (eHS) and

the physical converter shall be compared. Furthermore few techniques for

optimizing the switch conductance for the Pejovic discrete time switch model

shall be discussed in more details in Chapter 4.

1.8

Conclusion

A brief introduction to circuit simulation and

real time simulation of power electronic converters is provided in this

chapter. The chapter introduces some of the current trends in real time

simulation and also familiarizes the reader with the basics of RTS. The chapter

also introduces some switch models which are often used in the RTS of

electrical systems. Certain constraints in the RTS of power electronic systems

are also discussed, this chapter also reckons with related work done by other

researchers and gives a glimpse of the work that shall be done to complete this

thesis.