BEng (Hons) Electrical Electronic Engineering

TM625: Electronics and Control

Assignment 1

S13302

Contents

Table of Figures. 3

Abbreviations. 4

Task 1. 5

1. Weighted resistor DAC.. 5

2. R-2R DAC.. 6

3. Successive Approximation ADC.. 7

Task 2. 8

1. Explain circuit operation and modes. 8

2. Acquisition time. 9

3. Aperture time. 10

4. Drift Rate. 10

5. Settling time. 11

6. Hold step. 11

7. Turn – off time. 12

8. Calculate the time required for the capacitor voltage to reach a value within 1 percent of the input voltage. 13

Task 3. 14

1. TF = (2S+9)/(S2+2S+4), Gain of 2. 14

2. PID.. 15

3. PI 17

4. PD.. 19

5. Comparison of the performance of PI, PD and PID systems. 20

Task 4. 20

References. 21

Table of Figures

Figure 1: Weighted Resistor DAC Circuit 5

Figure 2: R-2R Ladder DAC Circuit 6

Figure 3: Successive Approximation ADC.. 7

Figure 4: Sample and hold circuit 8

Figure 5: Acquisition time graph.. 9

Figure 6: Aperture Time Graph.. 10

Figure 7: Drift Rate Graph.. 10

Figure 8: Settling Time Graph.. 11

Figure 9: Hold Step Graph.. 11

Figure 10: 12

Figure 11: RC Time Constant Table. 13

Figure 12: Transfer Function System.. 14

Figure 13: PID System Response. 14

Figure 14: PID Steady State Error 14

Figure 15: PID Values. 14

Figure 16: PID System.. 15

Figure 17: PID Response. 15

Figure 18: PID Gain.. 15

Figure 19: PID Steady State Error 15

Figure 20: PID Derivative. 15

Figure 21: PID Intergrator 16

Figure 22: PI System.. 16

Figure 23: PI System Response. 16

Figure 24: PI Steady State Error 16

Figure 25: PI Integrator 17

Figure 26: PI Gain.. 17

Figure 27: PI Derivative. 17

Figure 28: PD System.. 18

Figure 29: PD System Response. 18

Figure 30: PD Steady State Error 18

Figure 31: PD Integrator 18

Figure 32: PD Gain.. 18

Figure 33: PD Derivative. 18

Figure 34: Flash ADC Circuit Build. 19

Figure 35: Flash ADC Circuit Build. 19

Figure 36: Flash LEDs. 19

Abbreviations

DAC

Digital to Analogue Converter

ADC

Analogue to Digital Converter

MSB

Most significant bit

LSB

Least significant bit

SAR

Successive Approximation Register

FET

Field-effect transistor

PID

Proportional–Integral–Derivative Controller

Task 1

1. Weighted resistor DAC

Figure 1: Weighted Resistor DAC Circuit

The weighted resistors DAC circuit consists of resistors and an operational amplifier. Vout is the inverted sum of all the input voltages. If the values of the input resistors are set to multiples of two e.g. 1.25kohm, 2.5kohm, 5kohm, 10kohm, the output voltage would be equal to the sum of the input voltages multiplied by the ratio of input resistors and feedback resistor, V1*(10k/1.25k), V2*(10k/2.5k), V3*(10k/5k) and V4*(10k/10k).

Therefore,

V1 corresponds to the most significant bit (MSB) while V3 corresponds to the least significant bit (LSB).

2. R-2R DAC

The circuit for a 4-bit DAC using binary weighted resistor network is shown below:

Figure 2: R-2R Ladder DAC Circuit

An alternative to the Weighted Resistor DAC is the R-2R Ladder DAC. This type of DAC uses two values, R and 2 * R. when each input is supplied with a logic level 0 or a logic level 1 the output will be the voltage equivalent and the binary input. Its advantage of the weighted resistor DAC is that it has fewer different values.

The output can be given from the equation:

Where:

· Rf = R9 (20,000Ohms)

· Ra = R7 (10,000Ohms)

· N = number in decimal form i.e. 1001 = 9.

· n = number of bits in the system i.e. 4 bits in total.

· Vr = reference voltage, i.e. 5V

Therefore, to calculate the output if the binary input is 1001 would be;

3. Successive Approximation ADC

Figure 3: Successive Approximation ADC

The Successive Approximation ADC is a convertor that continuously converts an analogue signal into a digital output by a binary search method. The SAR ADC start by trying all the values of bits starting the MSB and finishing with the LSB.

For example, a SAR ADC with 4-bit resolution.

Vref = 1V

Vin = 0.6V.

Vadc = internal comparator voltage

The ADC starts with the MSB (Bit-3). Vref is divided by 2 and compared with Vin. As Vin is greater than Vref/2, it turns MSB to a logic 1.

1

X

X

X

The next calculation is for the MSB-1 (bit-2), Vin is compared to Vadc = Vref/2+Vref/4 = 0.5+0.25V = 0.75. As Vin < Vadc (0.75V) bit 2 is turned off. 1 0 X X For MSB-2 (bit-1) is compared with Vref/2 + Vref/8 = 0.625. as 0.6V < 0.625, the MSB is turned off. 1 0 0 X For MSB-3 (bit-0) is compared with Vref/2 + Vref/16 = 0.5625. as 0.6V > 0.5625, the MSB is turned on.

1

0

0

1

Task 2

Figure 4: Sample and hold circuit

1. Explain circuit operation and modes

The sample and hold circuit is used to capture an analogue voltage. There are two modes – sample (also known as track) and hold, below is a description of the operation of each.

In the sample mode, the sample control node is held to a logic 1 – the buffered input voltage flows the FET and charges the capacitor. In this made the output voltage will match the input voltage.

In the hold mode, when the sample control node is a logic 0, the FET is turned off. At this point the capacitor is disconnected from the input circuitry and retains the sampled voltage, this is then slowly discharged through the resistor and the op-amp to create a Vout.

2. Acquisition time

Figure 5: Acquisition time graph

The acquisition time is the length of time that the circuit must remain in the sample mode to acquire a full-scale output. The maximum acquisition time arises when the hold capacitor charges to a full-scale voltage change. This period depends on the size of the hold capacitor. The acquisition time can be reduced by choosing a smaller value capacitor, however this will also increase discharge rate.

3. Aperture time

Figure 6: Aperture Time Graph

The aperture time, is the delay between the hold signal being applied and the input signal being disconnected from the hold capacitor.

4. Drift Rate

Figure 7: Drift Rate Graph

This affect is known as droop rate expressed in V/us, during the hold mode there are errors in the hold capacitor, amplifiers and switch. If a leakage current flows in or out of the hold capacitor, this would slowly reduce or increase the voltage in the capacitor.

5. Settling time

Figure 8: Settling Time Graph

The settling time is the time taken for the output voltage to stabilise within a specified error band after a hold command has been given.

6. Hold step

Figure 9: Hold Step Graph

The hold step is the voltage at the output due to the sample-to-hold transition. It is caused by a transfer of charge to the hold capacitor due to the opening of the switch.

7. Turn – off time

Figure 10:

8. Calculate the time required for the capacitor voltage to reach a value within 1 percent of the input voltage.

· ON resistance = 30?

· C1 = 1µF

Time Constant

RC Value

Voltage percentage of max.

0.5 time constant

0.5T = 0.5RC

39.3%

0.7 time constant

0.7T = 0.7RC

50.3%

1.0 time constant

1T = 1RC

63.2%

2.0-time constants

2T = 2RC

86.5%

3.0-time constants

3T = 3RC

95.0%

4.0-time constants

4T = 4RC

98.2%

5.0-time constants

5T = 5RC

99.3%

Figure 11: RC Time Constant Table

The formula to calculate the time the voltage in the capacitor charges to within 1 percent of the input voltage is:

Therefore,

Task 3

1. TF = (2S+9)/(S2+2S+4), Gain of 2

Figure 12: Transfer Function System

Figure 13: PID System Response

The graph above shows the system response, settling at around 7 seconds.

Figure 14: PID Steady State Error

The graph above shows a steady state error of 0.0001

Figure 15: PID Values

P = 0.2222222222, I = 0.00000000001

D = 0.00000000001

2. PID System

Figure 16: PID System

Figure 17: PID Response

The above graph is the response of the PID system, shown to settle at around 8 seconds.

Figure 18: PID Gain

G = 0.1

Figure 19: PID Steady State Error

The above graph is the steady state error of the PID system, with an error of 0.0001.

Figure 20: PID Derivative

D = 50

Figure 21: PID Intergrator

I = 0.1749

3. PI System

Figure 22: PI System

Figure 23: PI System Response

The graph above is the response of the PI system, shown to settle at around 8 seconds.

Figure 24: PI Steady State Error

The graph above is the steady state error of the PID system, with an error of 0.0

Figure 25: PI Integrator

I = 0.1749

Figure 26: PI Gain

G = 0.1

Figure 27: PI Derivative

D = 0

4. PD System

Figure 28: PD System

Figure 29: PD System Response

The graph above is the response of the PD system, shown to settle at around 9 seconds.

Figure 30: PD Steady State Error

The graph above is the steady state error of the PID system, with an error of 0.0008

Figure 31: PD Integrator

Figure 32: PD Gain

Figure 33: PD Derivative

5. Comparison of the performance of PI, PD and PID systems

The PI, PD and PID systems

Task 4

Figure 34: Flash ADC Circuit Build

Figure 35: Flash ADC Circuit Build

Figure 36: Flash LEDs

References

Figure 5-9 – http://www.analog.com/media/en/training-seminars/tutorials/MT-090.pdf